full adder

we proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.

在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。

First, the static adder, transmision function adder and static Energy-Recovery full adder are realized in the subthreshold circuit.

首先，进行了静态加法器、传输功能加法器和静态能量恢复加法器的亚阈值电路实现。

Design and test of a high speed PRNs digital full adder

高速PRNS数母全加器的设计及测试原则

A High Speed Unit of Full Adder

一种高速全加器运算单元

Generalized Full Adder in Array Multiplier Design Model Application

一般化全加器在阵列乘法器设计中的典型应用

then, based on this t gate, the 2-5 mixed-valued/ ten-valued full adder and full subtracter are designed directly by the truth tables.

然后，在此基础上，按真值表直接设计2-5混值/十值全加器和全减器的运算电路。

Full adders are discussed, and a multiplexer based full adder is designed.

文章讨论几种全加器的设计, 并设计了一种基于数据选择器的全加器.

A Dynamic Full Adder Circuit Based on Single Electron Transistors

基于单电子晶体管的动态全加器电路设计

a model of algorithm has been proposed for composite neural network and the classification results of high precision are obtained through a full adder ( fa) fostered by the model.

提出了一种复合神经网络的算法模型，用该模型训练全加器（FA）获得了高精度分类结果。

A new PRNs digital full adder algorithm and its implementation scheme

一种新的PRNS数母全加器算法及其实现方案

By analyzing every part of △∑ D/ A converter, it is demonstrated that power consumption is mainly produced by the full-adder and register of digital part.

通过对各个部分的功耗分析表明，电路功耗主要由数字部分的全加器和寄存器产生。

Based on logic gates of complementary single-electron transistor ( SET), three units are proposed as follows: full adder, shift register and ROM.

基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。

the full adder output is a binary number.

这个全加器输出是一个二进制数。

Design of a Novel Full Adder Architecture

一种新型全加器结构的设计

Using Full Adder to Design Code Conversion Circuit Xiong

利用集成全加器设计码制转换电路